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Databahn™ - NAND Flash PHY IP

Databahn Flash PHY is an optimized solution for high-speed NAND devices (ONFi 2 and Toggle). The architecture is a very robust design to enhance performance, data integrity, and minimize resources. The PHY attaches directly to the Databahn Flash controller proving a complete solution and maximizing the flash compatibility options. The architecture is a third generation soft PHY architecture with industry leading capture capabilities.

It is unique in that it will also support asynchronous devices such as ONFi1 and legacy device interfaces, through a bypass mode. The internal PHY connections use a modified DFI interface to the controller. Not having to use a DLL offers many advantages lower power, easier routing, reduced gate count and lower cost. Databahn Flash PHY supports all known flash interfaces, providing the maximum flexibility to your design, as well as savings, minimizing multiple designs.

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Key Features:
  • Ideal for ONFi2 and Toggle interfaces
  • FPGA Toggle and ONFi2 PHY
  • PHY SoC architectures (with/ without DLL)
  • Process technology agnostic (180nm and below)

Architecture

  • Seperate PLL
    • Use for multiple slices
  • Soft PHY slice
    • Highly reusable
  • Test Logic for at-speed test
  • 1 DLL resource (FPGA)
  • 1 PHY clock generator slice (8 data ports)
  • Low-resource solution
  • Clock reference
    • Minimally buffered PLL input to slice (source synchronous domain)
    • Normal clock tree for DFI, flop-to-flop timing
    • 8 bit data ports

Top Level Architecture
The architecture is designed to maximize the timing margin for layout, this is accomplished in the architecture by maximizing where and how the clock phases are generated and where they are partitioned.

 

FPGA and SoC Architecture

PHY Data Slice

Top Level Architecture

NAND Flash PHY Clock

Features

  • Works with ONFi2 and Toggle interfaces
  • SoC Toggle and ONFi PHY
  • FPGA Toggle and ONFi2 PHY
  • 2 PHY SoC architectures with or without DLL
  • Process technology agnostic (180nm and below)
  • Scalable to many multiple channels (Typ. 8 Data to 1 timing)
  • By-pass mode for Async support (Legacy)
  • Multiple drive strength support for New H.S Device
  • Base design has been verified by third generation DDR DRAM PHY
  • Altera FPGA support
    • Uses DLL resources
  • No DLL, simplified clocking methodology (SoC)
    • No 3rd party core IP
  • Single PLL clock to derive multi phase capture
  • DFI derivate interface (DDR PHY Interface)
  • Flexible placement
  • Supports I/O's from most major suppliers
  • Advanced testability featuring built in at speed internal and external loopback. supporting full rate testing for ONFi 2 and Toggle
  • 8 bit data slice

Design Features

The PHY slices are programmable, providing the most robust timing possible. Each bit in the slice can be programmed for read capture relative to DQS + or - 1/2 clock. The output enable has a programmable output timing of 1/4 clock steps. Using DQS and DQ data the PHY will do pattern matching to make sure data is valid. Data alignment to other signals or to CLK can be achieved on a bit by bit bases down to 1/16th CLK. The timing and robustness of the PHY will assure compatibility to future enhancements to the ONFi 2 and Toggle specifications.

Deliverables

  • User guides and documentation
  • Behavioral Sim Model (verilog)
  • Full PHY RTL
  • Synthesis and STA scripts
  • Constraints
  • PHY layout guidelines
  • Basic testbench
  • DFI Monitor
  • Register configuration utility

Testability & Scan

The Denali PHY is 100% scannable for DFT. There are also 2 modes of internal and external loop-back testing.

BIST interface with available signals per data slice which can be use by ATE to get a pass/fail condition of the PHY. These signals are input/output ports of the PHY.

Register based loopback testing, under processor control, results are available in registers that give better information of the test results and enhanced controllability for choosing the clock phases used for the loopback testing.

Customers

"The ONFi source-synchronous interface can be found in all of Micron's 34nm MLC and SLC NAND products, providing customers with a fast read and write throughput that breaks through the interface bottlenecks of traditional NAND, which is especially important for today's NAND-based computing applications, such as SSDs. We believe Denali's NAND flash controller technology will provide a high-quality, hardware accelerated architecture to our customers, which leverages the features and functionality of our ONFi 2.1 devices."
Kevin Kilbuck
Director of Strategic NAND Marketing
Micron