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PCI Express Controller IP

Databahn PCIe is the industry leading IP solution which reduces risk and speeds time-to-market for deploying PCI Express (PCIe) interfaces in silicon. The Databahn PCIe controller IP conforms to the latest PCI-SIG specifications and has been validated against the leading PCIe verification tools and tested in silicon with commercial motherboards and adapter cards.

Databahn provides chip designers with the ability to configure the optimal PCIe controller IP for power, performance, and gate-count requirements. Pre-configured Databahn PCIe controller cores are also available to provide customers with off-the-shelf IP pre-designed specifically for consumer, enterprise, and mobile applications.

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Key Features:
  • Compliant with PCIe spec. v1.0a, 1.1, 2.0 & preliminary 3.0 (ver. 0.7)
  • Supports any 3rd party PHY compliant with the PIPE 2.0 & 3.0 specification
  • Compliant with Single-Root I/O Virtualization spec. v1.1
  • Configurable support for Root Complex, Endpoint, or dual-mode (switchable RC/EP) devices
  • Full ECN/ECR support

Architecture

Gen3 Operation
The core supports the latest PCIe 2.0, and PCIe 3.0 (ver. 0.7) specifications to enable up to sixteen 8.0 GT/s lane transfer rates. It will automatically negotiate speed and support link-retraining. The core is integrated to any Gen3 PHY via the PIPE 3.0 specifications and can be operated at 125MHz, 250MHz, or 500MHz with 32, 64, 128 or 256-bit datapaths.

Local Management Interface
The core provides a 32-bit management interface through which local software can read and write registers in the core. Software can access registers in the configuration space as well as local management registers (registers containing the configuration settings of the core, debug registers, status registers, etc.).

Host Application Layer Interface
Five distinct simple interfaces for master, memory, I/O, messaging, and interrupt transactions hide PCIe complexity. The memory Read/Write interface is for access to memory controllers or DMA. The master Read/Write interface is to initiate requests from the Endpoint as a bus master. The I/O interface support PCIe I/O transactions. The messaging interface supports customer messaging across PCIe and the interrupt interface supports all interrupts from the user application to the Databahn PCIe core.

High-Level Databahn PCIe Architecture

High Level Databahn PCIe Diagram

 

Features

The Databahn-PCIe core includes these features:

Single-Root I/O Virtualization
The Databahn-PCIe core provides a Gen 3 16-lane architecture in full support of the latest Address Translation Service (ATS) specification, Single-Root I/O Virtualization (SR-IOV) specification, including Internal Error Reporting, ID Based Ordering, TLP Processing Hints (TPH), Optimized Buffer Flush/Fill (OBFF), Atomic Operations, Re-Sizable BAR, Extended TAG Enable, Dynamic Power Allocation (DPA, and Latency Tolerance Reporting (LTR). SR-IOV is an optional capability that can be used with PCIe 1.1, 2.0, and 3.0 configurations.

Dual-mode operation
Each instance of the core can be configured as an Endpoint (EP) or Root Complex (RC).

Power management
The core supports PCIe link power states L0, L0s and L1 with only the main power. With auxiliary power, it can support L2 and L3 states.

Interrupt support
The core supports all the three options for implementing interrupts in a PCIe device: Legacy, MSI and MSIx modes. In the Legacy mode, it communicates the assertion and de-assertion of interrupt conditions on the link using Assert and De-assert messages. In the MSI mode, the core signals interrupts by sending MSI messages upon the occurrence of interrupt conditions. In this mode, the core supports up to 32 interrupt vectors per function, with per-vector masking. Finally, in the MSI-X mode, Databahn supports up to 2048 distinct interrupt vectors per function with per-vector masking.

Credit Management
The core performs all the link-layer credit management functions defined in the PCIe specifications. All credit parameters are configurable.

Configurable Flow-Control Updates
The core allows flow control updates from its receive side to be scheduled in a flexible manner, thus enabling the user to make tradeoffs between credit update frequency and its bandwidth overhead. Configurable registers control the scheduling of flow-control update DLLPs.

Replay Buffer
Databahn incorporates fully configurable link-layer reply buffers for each link designed for low latency and area. The core can maintain replay state for a configurable number of outstanding packets.

Host Interface
The datapath on the host interface is configurable to be 32, 64, 128 or 256-bits. It may be AXI or Host Application Layer (HAL) interface.

Verification Environment

The Databahn PCIe controller IP has been validated against the leading PCIe verification tools PureSpec™ and PureSuite™. PureSpec is a predictable verification solution for protocol compliance and enables verification planning and coverage-driven verification closure. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design.

PureSuite is the industry's most complete compliance suite for exercising designs and measuring compliance with the PCIe specification, and ensuring interoperability with other PCIe designs. Used with the PureSpec™ verification IP product, PureSuite provides a comprehensive, automated solution for functional verification of PCI Express designs.

Databahn PCIe System Level Diagram

 

Interoperability

The Databahn PCIe controller IP is silicon proven and shipping in customer production, including volume deployment in 10G network interface cards by major server vendors. Databahn-PCIe has been extensively verified against LeCroy® protocol analyzers, and tested in silicon with numerous chipsets and components such as:

  • Intel® Nehalem, Seaberg (5400)
  • Intel® Lindenhurst, Blackford, Greencreek, Tumwater
  • Serverworks®/Broadcom® ID0234
  • Nvidia® CK804, MCP67D, MCP65
  • Nvidia® CK804, MCP67D, MCP65
  • ATI® RS485, Hammerhead
  • PLX® PEX8533, PEX8525

Customers

"Our systems are deployed in mission critical applications and require superior performance, scalability, and reliability. After examining the available solutions in the industry, it was clear that Denali was more than capable of delivering a PCI Express 3.0 controller with the critical features that we needed. Not only has Denali met our functional and performance requirements, but their reputable technology, verification expertise and strong customer reputation made them a valued supplier."
Peg Williams
Sr. VP of R&D
Cray, Inc.

"Denali's PCIe core and PureSpec verification IP are integral enablers in meeting the PCIe Gen 2.0 specifications. Today's demanding data center networks address their increasing traffic needs by incorporating our latest accelerated 1Gb and 10Gb Ethernet products. Denali's reputation and track record speaks volumes for creating and delivering high-quality, complete IP solutions for the latest process technologies."
Terry Hulett
VP of Engineering
NetEffect

"To scale network performance to 10Gbps and beyond, the NFP-3240 offers a fully compliant PCIe v2.0 implementation including SR-IOV with 256 queues for network I/O co-processing in heterogeneous IA/x86 designs. When faced with the important decision as to which IP vendor has the most reputable and silicon-proven PCI Express IP, Denali Software was the preferred vendor that met our critical high throughput and feature requirements. We rely on Denali's high-quality, interoperable design and verification IP solutions and excellent customer support to meet the PCIe 2.0 and IOV specifications, our product development timeframes, and achieve a competitive advantage."
Jim Finnegan
Sr. Vice President of Silicon Engineering
Netronome

"Current chipsets demand higher-bandwidth support and chip-to-chip interconnectivity and Denali's IP products support the next-generation protocol requirements for design and verification of PCI Express systems. Denali's IP products help us streamline our design cycles and provide a clean roadmap for incorporating the latest specifications for our deployment of PCI Express technology."
John Sherman
Logic Design Manager
Engenio Storage Group
LSI Logic